The present invention relates to a signal modulator applied for digital data transmission in a mobile communication system, for example, and particularly to a GMSK (Gaussian Minimum Shift Keying) modulator having a high power efficiency, suitable to be applied for portable terminals needing low power consumption.
FIGS. 8(A) to 8(C) are schematic diagrams illustrating configurations of the GMSK modulator.
In a GMSK modulator of FIG. 8(A), a data signal 901 is processed through a Gaussian filter 902 (to be described afterwards) for restricting its frequency band, and supplied to a VCO (Voltage Controlled Oscillator) 903. A GMSK signal 904, which is a continuous radio wave having a constant envelope and frequency-modulated with a Gaussian filtered signal, namely, the data signal 901 after processing by the Gaussian filter 902, is obtained from the VCO 903. The configuration of FIG. 8(A) is basic and simple, but it is said to be difficult to apply in a small and high frequency device such as a portable terminal, because of the difficulty for of obtaining a VCO having a sufficient accuracy.
Therefore, the frequency modulation by the VCO 903 of FIG. 8(A) is replaced with a phase modulation of integration of the Gaussian filtered signal, performed by an integrator 905 and a phase modulator 906 in the configuration of FIG. 8(B), since the frequency is a differential of the phase.
Further, in the configuration of FIG. 8(C), the order of the Gaussian filter 902 and the integrator 905 of FIG. 8(B) is inverted for convenience of digital data processing, making use of a fact that the integration and the Gaussian filter operation has a linear relation.
Now, Gaussian filter operation is described, wherein signal values are normalized on a time axis for restricting frequency band.
FIG. 9 is a block diagram illustrating a Gaussian filter of four stages realized with a transversal type filter, comprising three delay elements 602, four multipliers 603 and an adder 604.
Four signal values of an input signal 601 ranged in order on a time axis are obtained at the same time by the three delay elements 602. Each of the four signal values is multiplied by each of the four multipliers 603 with each corresponding impulse response value h.sub.0 to h.sub.3 of the Gaussian filter to be added by the adder 604. Thus, the Gaussian filtered signal of the input signal 601 is obtained from the adder 604, normalized on the time axis, that is, in a frequency domain.
A prior example of a GMSK modulator according to the configuration of FIG. 8(C) is disclosed in a Japanese patent application entitled "Quadrature GMSK modulator", laid open as a Provisional Publication No. 23542/'92, whereof a block diagram is illustrated in FIG. 10.
Referring to FIG. 10, the prior GMSK modulator comprises;
a shift register 204 supplied with an input data signal 201, each bit thereof indicating a phase quadrant variation between .+-..pi./2,
an up-down counter 203 for integrating logic of one of parallel outputs of the shift register 204,
an n-bit counter 205 for counting pulses of a sampling clock 202 having n times the bit rate of the data signal 201, and supplying a shift signal to the shift counter at each n cycles of the sampling clock 202,
a first and a second ROM (Read Only Memory) 206 and 206', read address thereof indicated by parallel outputs of the up-down counter 203, the shift register 204 and the n-bit counter 205,
a first and a second D/A (Digital to Analog) converter 207 and 207', each supplied with data read-out from each of the first and the second ROM 206 and 206',
and a quadrature modulator 208 for outputting a GMSK signal 209 modulated with outputs of the first and the second D/A converter 207 and 207'.
A phase angle corresponding to integration of the data signal 201 and its time variation, defining input data of the Gaussian filter 902 of FIG. 8(C), are indicated by parallel outputs of the up-down counter 203 and the shift register 204. Sampling timings are indicated by parallel outputs of the n-bit counter 205.
In the first and the second ROM 206 and 206', an in-phase value and a quadrature value of each sampling timing of the Gaussian filtered signal corresponding to the input data are prepared in respective corresponding addresses.
The in-phase value and the quadrature value are read out at each sampling timing according to the above parallel outputs, and converted into analog values by the first and the second D/A converter 207 and 207', respectively, to be supplied to the quadrature modulator 208.
Thus, a GMSK signal 209 is obtained from the quadrature modulator 208, in the prior GMSK modulator of FIG. 10.
However, frequency of the sampling clock 202, according whereto the n-bit counter 205, the first and the second ROM 206 and 206', and the first and the second D/A converter 207 and 207' operate, must be sufficiently high compared to the bit rate of the data signal 201, which results in a considerable power consumption, in the prior GMSK modulator of FIG. 10.
This is because the GMSK signal generally takes wider frequency band than other linear modulation signals, and so, a high frequency sampling, more than four times the data rate, is required in order to prevent aliasing distortion caused by digital processing.